Publications of the ISIP Laboratory

Book Chapters

2015

  • F. Leduc-Primeau, V. C. Gaudet, and W. J. Gross, “Stochastic Decoders for LDPC Codes”, Chapter in Advanced Hardware Design for Error Correcting Codes, C. Chavet and P. Coussy eds., Springer, 2015, pp. 105-128. (doi) (url)

  • G. Sarkis and W. J. Gross, “Implementation of Polar Decoders”, Chapter in Advanced Hardware Design for Error Correcting Codes, C. Chavet and P. Coussy eds., Springer, 2015, pp. 33-45. (doi) (url)

2013

  • B. Mihajlović, W. J. Gross, and Ž. Žilic, “Software Debugging Infrastructure for Multi-Core Systems-on-Chip”, Chapter in Multicore Technology: Architecture, Reconfiguration and Modeling, M. Y. Qadri and S. J. Sangwine eds., CRC Press, 2013. (url)

Journal Papers

2016

  • C. Condo, P. Giard, F. Leduc-Primeau, G. Sarkis, and W. J. Gross, “A 9.96 dB NCG FEC scheme and 164 bits/cycle low-complexity product decoder architecture”, IEEE Transactions on Signal Processing, October 2016, submitted. (url)

  • K. Boga, F. Leduc-Primeau, N. Onizawa, T. Hanyu, and W. J. Gross, “A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception”, Journal of Signal Processing Systems, Springer, vol. PP, October 2016, to appear. (doi)

  • P. Giard, A. Balatsoukas-Stimming, G. Sarkis, C. Thibeault, and W. J. Gross, “Fast Low-Complexity Decoders for Low-Rate Polar Codes”, Journal of Signal Processing Systems, Springer, vol. PP, March 2016, to appear. (doi) (url)

  • P. Giard, G. Sarkis, C. Leroux, C. Thibeault, and W. J. Gross, “Low-Latency Software Polar Decoders”, Journal of Signal Processing Systems, Springer, vol. PP, 2016, pp. 1-15, to appear. (doi) (url)

  • S. A. Hashemi, C. Condo, and W. J. Gross, “A Fast Polar Code List Decoder Architecture Based on Sphere Decoding”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 12, December 2016, pp. 2368-2380. (doi) (url)

  • P. Giard, G. Sarkis, C. Thibeault, and W. J. Gross, “Multi-Mode Unrolled Hardware Architectures for Polar Decoders”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 9, September 2016, pp. 1443-1453. (doi) (url)

  • N. Onizawa, D. Katagiri, W. J. Gross, and T. Hanyu, “Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips”, IEEE Transactions on Nanotechnology, vol. 15, no. 5, September 2016, pp. 705-714. (doi)

  • A. Ardakani, F. Leduc-Primeau, N. Onizawa, T. Hanyu, and W. J. Gross, “VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, August 2016, submitted. (url)

  • G. Sarkis, I. Tal, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, “Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes”, IEEE Transactions on Communications, vol. 64, no. 7, July 2016, pp. 2732-2745. (doi) (url)

  • F. Escribano, G. Kaddoum, A. Wagemakers, and P. Giard, “Design of a New Differential Chaos Shift Keying System For Continuous Mobility”, IEEE Transactions on Communications, vol. 64, no. 5, May 2016, pp. 2066-2078. (doi)

  • S. Hemati, F. Leduc-Primeau, and W. J. Gross, “A Relaxed Min-Sum LDPC Decoder With Simplified Check Nodes”, IEEE Communications Letters, vol. 20, no. 3, March 2016, pp. 422-425. (doi)

  • F. Leduc-Primeau, V. Gripon, M. G. Rabbat, and W. J. Gross, “Fault-Tolerant Associative Memories Based on $c$-Partite Graphs”, IEEE Transactions on Signal Processing, vol. 64, no. 4, February 2016, pp. 829-841. (doi) (url)

  • G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, “Fast List Decoders for Polar Codes”, IEEE Journal on Selected Areas in Communications - Special Issue on Recent Advances In Capacity Approaching Codes, vol. 34, no. 2, February 2016, pp. 318-328. (doi) (url)

  • Y. El-Kurdi, D. Fernández, W. J. Gross, and D. D. Giannacopoulos, “Acceleration of the Finite-Element Gaussian Belief Propagation Solver Using Minimum Residual Techniques”, IEEE Transactions on Magnetics, vol. 52, no. 3, March 2016, pp. 1-4. (doi)

  • N. Onizawa, H. Jarollahi, T. Hanyu, and W. J. Gross, “Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 1, March 2016, pp. 13-24. (doi)

  • M. Martina, C. Condo, M. Ruo Roch, and G. Masera, “Computation reduction for turbo decoding through window-skipping”, IET Electronics Letters, vol. 52, February 2016, pp. 202-204. (doi)

2015

  • C. Condo and W. J. Gross, “Pseudo-random Gaussian distribution through optimized LFSR permutations”, IET Electronics Letters, vol. 51, December 2015, pp. 2098-2100. (doi)

  • Y. El-Kurdi, M. M. Dehnavi, W. J. Gross, and D. Giannacopoulos, “Parallel finite element technique using Gaussian belief propagation”, Computer Physics Communications, Elsevier, vol. 193, August 2015, pp. 38-48. (doi)

  • P. Giard, G. Sarkis, C. Thibeault, and W. J. Gross, “237 Gbit/s Unrolled Hardware Polar Decoder”, IET Electronics Letters, vol. 51, May 2015, pp. 762-763. (doi) (url)

  • H. Jarollahi, V. Gripon, N. Onizawa, and W. J. Gross, “Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 4, April 2015, pp. 642-653. (doi)

  • F. Leduc-Primeau, F. R. Kschischang, and W. J. Gross, “Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations”, IEEE Transactions on Communications, March 2015, submitted. (url)

  • N. Onizawa, D. Katagiri, K. Matsumiya, W.J. Gross, and T. Hanyu, “Gabor Filter Based on Stochastic Computation”, IEEE Signal Processing Letters, vol. 22, no. 9, September 2015, pp. 1224-1228. (doi) (url)

2014

  • H. Jarollahi, N. Onizawa, V. Gripon, N. Sakimura, T. Sugibayashi, T. Endoh, H. Ohno, T. Hanyu, and W. J. Gross, “A Non-Volatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 4, no. 4, December 2014, pp. 460-474. (doi)

  • A. J. Raymond and W. J. Gross, “A Scalable Successive-Cancellation Decoder for Polar Codes”, IEEE Transactions on Signal Processing, vol. 62, no. 20, October 2014, pp. 5339-5347. (doi)

  • H. Jarollahi, N. Onizawa, V. Gripon, and W. J. Gross, “Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks”, Journal of Signal Processing Systems, Springer, vol. 76, no. 3, September 2014, pp. 235-247. (doi)

  • A. Balatsoukas-Stimming, A.J. Raymond, W.J. Gross, and A. Burg, “Hardware Architecture for List Successive Cancellation Decoding of Polar Codes”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 8, August 2014, pp. 609-613. (doi) (url)

  • G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, “Fast Polar Decoders: Algorithm and Implementation”, IEEE Journal on Selected Areas in Communications, vol. 32, no. 5, May 2014, pp. 946-957. (doi) (url)

  • N. Onizawa, S. Matsunaga, V. C. Gaudet, W. J. Gross, and T. Hanyu, “High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 3, March 2014, pp. 865-876. (doi)

  • Y. El-Kurdi, W.J. Gross, and D. Giannacopoulos, “Parallel Multigrid Acceleration for the Finite-Element Gaussian Belief Propagation Algorithm”, IEEE Transactions on Magnetics, vol. 50, no. 2, February 2014, pp. 581-584. (doi)

  • K. Cushon, S. Hemati, C. Leroux, S. Mannor, and W.J. Gross, “High-Throughput Energy-Efficient LDPC Decoders Using Differential Binary Message Passing”, IEEE Transactions on Signal Processing, vol. 62, no. 3, February 2014, pp. 619-631. (doi)

2013

  • A. Ciobanu, S. Hemati, and W. J. Gross, “Adaptive Multiset Stochastic Decoding of Non-binary LDPC Codes”, IEEE Transactions on Signal Processing, vol. 61, no. 16, 2013, pp. 4100-4113. (doi)

  • G. Sarkis and W. J. Gross, “Increasing the Throughput of Polar Decoders”, IEEE Communications Letters, vol. 17, no. 4, 2013, pp. 725-728. (doi)

  • G. Sarkis, S. Hemati, S. Mannor, and W. J. Gross, “Stochastic Decoding of LDPC Codes over GF(q)”, IEEE Transactions on Communications, vol. 61, no. 3, 2013, pp. 939-950. (doi)

  • F. Leduc-Primeau, S. Hemati, S. Mannor, and W. J. Gross, “Relaxed Half-Stochastic Belief Propagation”, IEEE Transactions on Communications, vol. 61, no. 5, 2013, pp. 1648-1659. (doi)

  • F. D. Côté, I. N. Psaromiligkos, and W. J. Gross, “On the Chandra-Poram-Bose SEP Expression for Coherent Orthogonal M-FSK”, International Journal of Communication Systems, vol. 27, no. 10, 2014, pp. 2092-2096. (doi) (url)

  • N. Onizawa, S. Matsunaga, V. C. Gaudet, W. J. Gross, and T. Hanyu, “High-Throughput CAM Based on a Synchronous Overlapped Search Scheme”, IEICE Electronics Express, vol. 10, no. 7, 2013, p. 20130148. (url)

  • C. Leroux, A. J. Raymond, G. Sarkis, and W. J. Gross, “A Semi-Parallel Successive-Cancellation Decoder for Polar Codes”, IEEE Transactions on Signal Processing, vol. 61, no. 2, January 2013, pp. 289-299. (doi)

2012

2011

  • A. Naderi, S. Mannor, M. Sawan, and W. J. Gross, “Delayed Stochastic Decoding of LDPC Codes”, IEEE Transactions on Signal Processing, vol. 59, no. 11, November 2011, pp. 5617-5626. (doi)

  • M. N. Sakib, T. Huang, W. J. Gross, and O. Liboiron-Ladouceur, “Low-Density Parity-Check Coding in Ultra-Wideband-Over-Fiber Systems”, IEEE Photonics Technology Letters, vol. 23, no. 20, October 2011, pp. 1493-1495. (doi)

  • F. D. Côté, I. N. Psaromiligkos, and W. J. Gross, “GNSS Modulation: A Unified Statistical Description”, IEEE Transactions on Aerospace and Electronic Systems, vol. 47, no. 3, July 2011, pp. 1814-1836. (doi)

  • M. Arzel, C. Lahuec, C. Jego, W. J. Gross, and Y. Bruned, “Stochastic Multiple Stream Decoding of Cortex Codes”, IEEE Transactions on Signal Processing, vol. 59, no. 7, July 2011, pp. 3486-3491. (doi)

  • M. N. Sakib, V. Mahalingam, W. J. Gross, and O. Liboiron-Ladouceur, “Optical Front-End for Soft-Decision LDPC Codes in Optical Communication Systems”, IEEE/OSA Journal of Optical Communications and Networking, vol. 3, no. 6, May 2011, pp. 533-541. (doi)

  • S. Sharifi Tehrani, A. Naderi, G.-A. Kamendje, S. Mannor, and W. J. Gross, “Tracking Forecast Memories for Stochastic Decoding”, Journal of Signal Processing Systems, Springer, vol. 63, no. 1, April 2011, pp. 117-127. (doi)

2010

  • Q. T. Dong, M. Arzel, C. Jego, and W. J. Gross, “Stochastic Decoding of Turbo Codes”, IEEE Transactions on Signal Processing, vol. 58, no. 12, December 2010, pp. 6421-6425. (doi)

  • K. Cushon, C. Leroux, S. Hemati, S. Mannor, and W. J. Gross, “A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 11, November 2010, pp. 893-897. (doi)

  • C. Winstead, S. Sharifi Tehrani, W. J. Gross, S. Mannor, S. Howard, and V. C. Gaudet, “Relaxation Dynamics in Stochastic Iterative Decoders”, IEEE Transactions on Signal Processing, vol. 58, no. 11, November 2010, pp. 5955-5961. (doi)

  • S. Sharifi Tehrani, A. Naderi, G.-A. Kamendje, S. Hemati, S. Mannor, and W. J. Gross, “Majority-Based Tracking Forecast Memories for Stochastic LDPC Decoding”, IEEE Transactions on Signal Processing, vol. 58, no. 9, September 2010, pp. 4883-4896. (doi)

  • C. Leroux, S. Hemati, S. Mannor, and W. J. Gross, “Stochastic Chase Decoding of Reed-Solomon Codes”, IEEE Communications Letters, vol. 14, no. 9, September 2010, pp. 863-865. (doi)

  • D. M. Fernández, D. Giannacopoulos, and W. J. Gross, “Multicore Acceleration of CG Algorithms Using Blocked-Pipeline-Matching Techniques”, IEEE Transactions on Magnetics, vol. 46, no. 8, August 2010, pp. 3057-3060. (doi)

2009

  • J. J. Koo, A. C. Evans, and W. J. Gross, “3-D Brain MRI Tissue Classification on FPGAs”, IEEE Transactions on Image Processing, vol. 18, no. 12, December 2009, pp. 2735-2746. (doi)

  • C. Jego and W. J. Gross, “Turbo Decoding of Product Codes using Adaptive Belief Propagation”, IEEE Transactions on Communications, vol. 57, no. 10, October 2009, pp. 2864-2867. (doi)

  • D. M. Fernández, D. Giannacopoulos, and W. J. Gross, “Efficient Multicore Sparse Matrix-Vector Multiplication for FE Electromagnetics”, IEEE Transactions on Magnetics, vol. 45, no. 3, March 2009, pp. 1392-1395. (doi)

2008

  • S. Bi and W. J. Gross, “The Mixed-Radix Chinese Remainder Theorem and Its Applications to Residue Comparison”, IEEE Transactions on Computers, vol. 57, no. 12, December 2008, pp. 1624-1632. (doi)

  • S. Sharifi Tehrani, S. Mannor, and W. J. Gross, “Fully Parallel Stochastic LDPC Decoders”, IEEE Transactions on Signal Processing, vol. 56, no. 11, November 2008, pp. 5692-5703. (doi)

  • S. Sharifi Tehrani, C. Jego, B. Zhu, and W. J. Gross, “Stochastic Decoding of Linear Block Codes with High-Density Parity-Check Matrices”, IEEE Transactions on Signal Processing, vol. 56, no. 11, November 2008, pp. 5733-5739. (doi)

  • J. S. Beeckler and W. J. Gross, “Particle Graphics on Reconfigurable Hardware”, ACM Transactions on Reconfigurable Technology and Systems, vol. 1, no. 3, September 2008, pp. 15:1-15:27. (doi)

  • L. Boulianne, S. Al Assaad, M. Dumontier, and W. J. Gross, “GridCell: A Stochastic Particle-Based Biological System Simulator”, BMC Systems Biology, vol. 2, no. 1, July 2008, p. 2:66. (doi)

  • Y. El-Kurdi, D. M. Fernández, E. Souleimanov, D. Giannacopoulos, and W. J. Gross, “FPGA Architecture and Implementation of Sparse Matrix–Vector Multiplication for the Finite Element Method”, Computer Physics Communications, vol. 178, no. 8, April 2008, pp. 558-570. (doi)

2007

  • Y. El-Kurdi, D. Giannacopoulos, and W. J. Gross, “Hardware Acceleration for Finite-Element Electromagnetics: Efficient Sparse Matrix Floating-Point Computations with FPGAs”, IEEE Transactions on Magnetics, vol. 43, no. 4, April 2007, pp. 1525-1528. (doi)

  • W. J. Gross, F. R. Kschischang, and P. G. Gulak, “Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding”, IEEE Transactions on VLSI Systems, vol. 15, no. 3, March 2007, pp. 309-318. (doi)

2006

  • S. Sharifi Tehrani, W. J. Gross, and S. Mannor, “Stochastic Decoding of LDPC Codes”, IEEE Communications Letters, vol. 10, no. 10, October 2006, pp. 716-718. (doi)

  • W. J. Gross, F. R. Kschischang, R. Koetter, and P. G. Gulak, “Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes”, IEEE Transactions on Communications, vol. 54, no. 7, July 2006, pp. 1224-1234. (doi)

Prior to 2006

  • W. J. Gross, F. R. Kschischang, R. Koetter, and P. G. Gulak, “Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders”, Journal of VLSI Signal Processing, vol. 39, no. 1/2, January 2005, pp. 93-111. (doi)

  • E. Boutillon, W. J. Gross, and P. G. Gulak, “VLSI Architectures for the MAP Algorithm”, IEEE Transactions on Communications, vol. 51, no. 2, February 2003, pp. 175-185. (doi)

  • W. J. Gross, V. C. Gaudet, and P. G. Gulak, “Difference Metric Soft-Output Detection: Architecture and Implementation”, IEEE Transactions on Circuits and Systems II (Analog and Digital Signal Processing), vol. 48, no. 10, October 2001, pp. 904-911. (doi)

  • W. J. Gross and P. G. Gulak, “Simplified MAP Algorithm Suitable for Implementation of Turbo Decoders”, Electronics Letters, vol. 34, no. 16, 1998, pp. 1577-1158. (doi)

  • R. H. MacPhie, W. J. Gross, and I. Z. Lian, “The Impedance of a Centre-Fed Strip Dipole by the Poynting Vector Method”, IEEE Transactions on Antennas and Propagation, vol. 43, no. 2, March 1995, pp. 257-263. (doi)

Conference Papers

2017

  • L. Lugosch and W. J. Gross, “Neural Offset Min-Sum Decoding”, Proceedings of IEEE International Symposium on Information Theory (ISIT), July 2017, to appear. (url)

2016

  • C. Condo, F. Leduc-Primeau, G. Sarkis, P. Giard, and and W. J. Gross, “Stall Pattern Avoidance in Polynomial Product Codes”, Proceedings of IEEE Global Conference on Signal and Information Processing (GlobalSIP), December 2016, pp. 699-702, Arlington, VA, USA. (doi) (url)

  • P. Giard, A. Balatsoukas-Stimming, T. C. Müller, A. Burg, C. Thibeault, and W. J. Gross, “A Multi-Gbps Unrolled Hardware List Decoder for a Systematic Polar Code”, Proceedings of Asilomar Conference on Signals, Systems, and Computers, December 2016, pp. 1194-1198, Pacific Grove, CA, USA. (doi) (url)

  • A. Ardakani, F. Leduc-Primeau, N. Onizawa, T. Hanyu, and W. J. Gross, “VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing”, Proceedings of International Symposium on Turbo Codes & Iterative Information Processing (ITSC), September 5-9, 2016, pp. 216-220, Brest, FRA. (doi)

  • F. Leduc-Primeau and W. J. Gross, “Finite-Length Quasi-Synchronous LDPC Decoders”, Proceedings of International Symposium on Turbo Codes & Iterative Information Processing (ITSC), September 5-9, 2016, pp. 325-329, Brest, FRA. (doi) (url)

  • S. A. Hashemi, C. Condo, and W. J. Gross, “Simplified Successive-Cancellation List decoding of polar codes”, Proceedings of IEEE International Symposium on Information Theory (ISIT), July 2016, pp. 815-819, Barcelona, ESP. (doi)

  • P. Giard, G. Sarkis, A. Balatsoukas-Stimming, Y. Fan, C.-y. Tsui, A. Burg, C. Thibeault, and W. J. Gross, “Hardware Decoders for Polar Codes: An Overview”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2016, pp. 149-152, Montreal, QC, CAN. (doi) (url)

  • S. A. Hashemi, C. Condo, and W. J. Gross, “Matrix Reordering for Efficient List Sphere Decoding of Polar Codes”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2016, pp. 1730-1733, Montreal, QC, CAN. (doi) (url)

  • A. Ardakani, F. Leduc-Primeau, and W. J. Gross, “Hardware Implementation of FIR/IIR Digital Filters Using Integral Stochastic Computation”, Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), March 2016, pp. 6540-6544, Shanghai, CHN. (doi)

  • S. A. Hashemi, A. Balatsoukas-Stimming, P. Giard, C. Thibeault, and W. J. Gross, “Partitioned Successive-Cancellation List Decoding of Polar Codes”, Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), March 2016, pp. 957-960, Shanghai, CHN. (doi) (url)

2015

  • S. A. Hashemi, C. Condo, and W. J. Gross, “List Sphere Decoding of Polar Codes”, Proceedings of Asilomar Conference on Signals, Systems, and Computers, November 2015, pp. 1346-1350, Pacific Grove, CA, USA. (doi)

  • K. Boga, N. Onizawa, F. Leduc-Primeau, K. Matsumiya, T. Hanyu, and W. J. Gross, “Stochastic Implementation of the Disparity Energy Model for Depth Perception”, Proceedings of IEEE International Workshop on Signal Processing Systems (SiPS), October 2015, pp. 1-6, Hangzhou, CHN. (doi)

  • C. Condo and W. J. Gross, “Sparse Superposition Codes: A Practical Approach”, Proceedings of IEEE International Workshop on Signal Processing Systems (SiPS), October 2015, pp. 1-6, Hangzhou, CHN. (doi)

  • P. Giard, G. Sarkis, C. Thibeault, and W. J. Gross, “A 638 Mbps Low-Complexity Rate 1/2 Polar Decoder on FPGAs”, Proceedings of IEEE International Workshop on Signal Processing Systems (SiPS), October 2015, pp. 1-6, Hangzhou, CHN. (doi)

  • A. J. Wong, S. Hemati, and W. J. Gross, “Efficient implementation of structured long block-length LDPC codes”, Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2015, pp. 234-238, Toronto, ON, CAN. (doi)

  • N. Onizawa, D. Katagiri, K. Matsumiya, W.J. Gross, and T. Hanyu, “Frequency-flexible stochastic Gabor filter”, Proceedings of IEEE International Conference on Digital Signal Processing (DSP), July 2015, pp. 458-462, Singapore, SGP. (doi)

  • Y El-Kurdi, D. Fernández, W. J. Gross, and D. Giannacopoulos, “Acceleration of the Finite Element Gaussian Belief Propagation Solver Using Minimum Residual Techniques”, Proceedings of IEEE Conference on the Computation of Electromagnetic Fields (COMPUMAG), June 28-July 2, 2015, Montréal, QC, CAN. (url)

  • F. Leduc-Primeau, F. R. Kschischang, and W. J. Gross, “Energy optimization of LDPC decoder circuits with timing violations”, Proceedings of IEEE International Conference on Communications (ICC), June 8-12, 2015, pp. 412-417, London, GBR. (doi)

  • R. Danilo, H. Jarollahi, V. Gripon, P. Coussy, L. Conde-Canencia, and W.J. Gross, “Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27, 2015, pp. 2501-2504, Lisbon, PRT. (doi) (url)

  • R. Danilo, P. Coussy, L. Conde-Canencia, V. Gripon, and W. J. Gross, “Restricted Clustered Neural Network for Storing Real Data”, Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), ACM, May 20-22, 2015, pp. 205-210, Pittsburgh, PA, USA. (doi) (url)

2014

  • G. Sarkis, P. Giard, C. Thibeault, and W. J. Gross, “Autogenerating Software Polar Decoders”, Proceedings of IEEE Global Conference on Signal and Information Processing (GlobalSIP), December 3-5, 2014, pp. 6-10, Atlanta, GA, USA. (doi)

  • H. Jarollahi, N. Onizawa, V. Gripon, T. Hanyu, and W. J. Gross, “Algorithm and Architecture for a Multiple-Field Context-Driven Search Engine Using Fully-Parallel Clustered Associative Memories”, Proceedings of IEEE International Workshop on Signal Processing Systems (SiPS), October 20-22, 2014, pp. 1-6, Belfast, GBR. (doi)

  • G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, “Increasing the Speed of Polar List Decoders”, Proceedings of IEEE International Workshop on Signal Processing Systems (SiPS), October 20-22, 2014, pp. 1-6, Belfast, GBR. (doi) (url)

  • H. Jarollahi, N. Onizawa, T. Hanyu, and W. J. Gross, “Associative Memories Based on Multiple-Valued Sparse Clustered Networks”, Proceedings of IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 19-21, 2014, pp. 208-213, Bremen, DE. (doi) (url)

  • N. Onizawa, D. Katagiri, W. J. Gross, and T. Hanyu, “Analog-to-stochastic converter using magnetic-tunnel junction devices”, Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), July 2014, pp. 59-64. (doi)

  • K. Cushon, S. Hemati, S. Mannor, and W. J. Gross, “Energy-efficient gear-shift LDPC decoders”, Proceedings of IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), June 2014, pp. 219-223. (doi)

  • P. Giard, G. Sarkis, C. Thibeault, and W. J. Gross, “Fast Software Polar Decoders”, Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 4-9, 2014, pp. 7555-7559, Florence, ITA. (doi) (url)

  • F. Leduc-Primeau, V. Gripon, M. G. Rabbat, and W. J. Gross, “Cluster-based Associative Memories Built from Unreliable Storage”, Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 4-9, 2014, pp. 8370-8374, Florence, ITA. (doi) (url)

  • G. Kaddoum and P. Giard, “Analog Network Coding for Multi-User Spread-Spectrum Communication Systems”, Proceedings of IEEE Wireless Communications and Networking Conference (WCNC), April 2014, pp. 352-357, Istanbul, TUR. (doi) (url)

2013

  • A. J. Raymond and W. J. Gross, “Scalable Successive-Cancellation Hardware Decoder for Polar Codes”, Proceedings of 1st IEEE Global Conference on Signal and Information Processing (GlobalSIP), December 2013, pp. 1282-1285, Austin, TX, USA. (doi) (url)

  • H. Jarollahi, N. Onizawa, and W.J. Gross, “Selective Decoding in Associative Memories Based on Sparse-Clustered Networks”, Proceedings of 1st IEEE Global Conference on Signal and Information Processing (GlobalSIP), December 2013, pp. 1270-1273, Austin, TX, USA. (doi) (url)

  • Y. El-Kurdi, W. J. Gross, and D. Giannacopoulos, “Parallel Multigrid Acceleration for the Finite Element Gaussian Belief Propagation Algorithm”, Proceedings of IEEE Conference on the Computation of Electromagnetic Fields (COMPUMAG), June 30-July 4, 2013, Budapest, HUN. (url)

  • H. Jarollahi, V. Gripon, N. Onizawa, and W. J. Gross, “A Low-Power Content-Addressable-Memory Based on Clustered Sparse Networks”, Proceedings of 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), June 5-7, 2013, pp. 305-308, Washington, DC, USA. (doi)

  • H. Jarollahi, N. Onizawa, V. Gripon, and W. J. Gross, “Reduced-Complexity Binary-Weigh-Coded Associative Memories”, Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 26-31, 2013, pp. 2523-2527, Vancouver, BC, CAN. (doi)

  • N. Onizawa, W. J. Gross, and T. Hanyu, “Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems”, Proceedings of 19th International Symposium on Asynchronous Circuits and Systems (ASYNC), May 19-22, 2013, pp. 8-15, Santa Monica, CA, USA. (doi)

  • N. Onizawa and W. J. Gross, “Low-Power Area-Efficient Large-Scale IP Lookup Engine Based on Binary-Weighted Clustered Networks”, Proceedings of 50th Design Automation Conference (DAC), June 2-6, 2013, Austin, TX, USA. (doi)

  • N. Onizawa, W. J. Gross, and T. Hanyu, “Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating”, Proceedings of IEEE 43rd International Symposium on Multiple-Valued Logic (ISMVL), May 21-24, 2013, pp. 254-259, Toyama, JPN. (doi)

  • G. Sarkis and W. J. Gross, “Polar Codes for Data Storage Applications”, Proceedings of IEEE International Conference on Computing, Networking and Communications (ICNC), January 28-31, 2013, pp. 840-844, San Diego, CA, USA, Invited paper. (doi)

2012

  • A. Mishra, A. J. Raymond, L. G. Amaru, G. Sarkis, C. Leroux, P. Meinerzhagen, A. Burg, and W. J. Gross, “A Successive Cancellation Decoder ASIC for a 1024-bit Polar Code in 180nm CMOS”, Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), November 12-14, 2012, Kobe, JPN. (doi)

  • Y. El-Kurdi, D. Giannacopoulos, and W. J. Gross, “Parallel Solution of the Finite Element Method Using Gaussian Belief Propagation”, Proceedings of IEEE Conference of Electromagnetic Field Computation (CEFC), November 11-14, 2012, Oita, JPN, to appear.

  • F. Leduc-Primeau, A. J. Raymond, P. Giard, C. Thibeault, and W. J. Gross, “High-Throughput LDPC Decoding Using the RHS Algorithm”, Proceedings of Conference on Design and Architectures for Signal and Image Processing (DASIP), October 23-25, 2012, Karlsruhe, DEU. (url)

  • S. Sharifi Tehrani, P. Siegel, S. Mannor, and W. J. Gross, “Joint Stochastic Decoding of LDPC Codes and Partial Response Channels”, Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), October 17-19, 2012, pp. 13-18, Québec City, QC, CAN. (doi)

  • N. Onizawa, W. J. Gross, T. Hanyu, and V. Gaudet, “Clockless Stochastic Decoding of Low-Density Parity-Check Codes”, Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), October 17-19, 2012, pp. 143-148, Québec City, QC, CAN. (doi)

  • F. Leduc-Primeau and W. J. Gross, “Faulty Gallager-B Decoding with Optimal Message Repetition”, Proceedings of 50th Annual Allerton Conference on Communication, Control, and Computing (Allerton), October 1-5, 2012, pp. 549-556, Monticello, Illinois, USA. (doi)

  • V. Gripon, M. Rabbat, V. Skachek, and W. J. Gross, “Compressing Multisets using Tries”, Proceedings of IEEE Information Theory Workshop (ITW), September 3-7, 2012, pp. 642-646, Lausanne, CHE. (doi)

  • V. Gripon, V. Skachek, W. J. Gross, and M. Rabbat, “Random Clique Codes”, Proceedings of 7th International Symposium on Turbo Codes & Iterative Information Processing (ITSC), August 27-31, 2012, pp. 121-125, Gothenburg, SWE. (doi)

  • Y. El-Kurdi, D. Giannacopoulos, and W. J. Gross, “Relaxed Gaussian Belief Propagation”, Proceedings of IEEE International Symposium on Information Theory (ISIT), July 1-6, 2012, Cambridge, MA, USA. (doi)

  • R. Heloir, C. Leroux, S. Hemati, M. Arzel, and W. J. Gross, “Stochastic Chase Decoder for Reed-Solomon Codes”, Proceedings of 10th IEEE International NEWCAS Conference (NEWCAS), June 17-20, 2012, pp. 5-8, Montréal, QC, CAN. (doi)

  • H. Jarollahi, N. Onizawa, V. Gripon, and W. J. Gross, “Architecture and Implementation of an Associative Memory Using Sparse Clustered Networks”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 20-23, 2012, pp. 2901-2904, Seoul, KOR. (doi)

  • N. Onizawa, V. C. Gaudet, T. Hanyu, and W. J. Gross, “Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes”, Proceedings of 2012 IEEE 42nd International Symposium on Multiple-Valued Logic (ISMVL), May 2012, pp. 92-97, Victoria, BC, CAN. (doi)

2011

  • C. Leroux, I. Tal, A. Vardy, and W. J. Gross, “Architectures matérielles pour le décodage des codes polaires”, Proceedings of GRETSI Symposium on Signal and Image Processing, September 5-8, 2011, Bordeaux, FRA. (url)

  • Y. El-Kurdi, W. J. Gross, and D. Giannacopoulos, “Efficient Implementation of Gaussian Belief Propagation Solver for Large Sparse Diagonally Dominant Linear Systems”, Proceedings of IEEE Conference on the Computation of Electromagnetic Fields (COMPUMAG), July 12-15, 2011, Sydney, AUS.

  • D. M. Fernández, M. Mehri Dehnavi, W. J. Gross, and D. Giannacopoulos, “Alternate Parallel Processing Approach for FEM”, Proceedings of IEEE Conference on the Computation of Electromagnetic Fields (COMPUMAG), July 12-15, 2011, Sydney, AUS.

  • C. Leroux, I. Tal, A. Vardy, and W. J. Gross, “Hardware Architectures for Successive Cancellation Decoding of Polar Codes”, Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), May 22-27, 2011, pp. 1665-1668, Prague, CZE. (doi)

  • M. N. Sakib, A. J. Wong, W. J. Gross, and O. Liboiron-Ladouceur, “Decoding of Long-Block Soft Decision LDPC Codes for Optical Communication Systems”, Proceedings of ICO International Conference on Information Photonics, May 18-20, 2011, Ottawa, ON, CAN. (doi)

  • M. N. Sakib, V. Mahalingam, A. J. Wong, W. J. Gross, and O. Liboiron-Ladouceur, “Low Complexity Soft Decision Circuit for LDPC Decoders”, Proceedings of Conference on Lasers and Electro-Optics (CLEO), May 1-6, 2011, Baltimore, MD, USA. (url)

2010

  • F. Leduc-Primeau, S. Hemati, S. Mannor, and W. J. Gross, “Lowering Error Floors Using Dithered Belief Propagation”, Proceedings of IEEE Global Telecommunications Conference (GLOBECOM), December 6-10, 2010, pp. 1-6, Miami, FL, USA. (doi)

  • G. Sarkis, S. Hemati, S. Mannor, and W. J. Gross, “Relaxed Half-Stochastic Decoding of LDPC Codes over GF(q)”, Proceedings of 48th Annual Allerton Conference on Communication, Control, and Computing (Allerton), September 29 - October 1, 2010, pp. 36-41, Monticello, IL, USA. (doi)

  • V. C. Gaudet and W. J. Gross, “Switching Activity in Stochastic Decoders”, Proceedings of 40th IEEE International Symposium on Multiple-Valued Logic (ISMVL), May 26-28, 2010, pp. 167-172, Barcelona, ESP. (doi)

  • G. Sarkis and W. J. Gross, “Reduced-Latency Stochastic Decoding of LDPC Codes over GF(q)”, Proceedings of European Wireless Conference (EW), April 12-15, 2010, pp. 994-998, Lucca, ITA. (doi)

  • F. D. Côté, I. N. Psaromiligkos, and W. J. Gross, “On the Code Tracking Performance of GNSS Modulation”, Proceedings of 44th Annual Conference on Information Sciences and Systems (CISS), March 17-19, 2010, pp. 1-5, Princeton, NJ, USA. (doi)

2009

  • F. Leduc-Primeau, S. Hemati, W. J. Gross, and S. Mannor, “A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes”, Proceedings of IEEE Global Telecommunications Conference (GLOBECOM), November 30 - December 4, 2009, pp. 1-6, Honolulu, HI, USA. (doi)

  • D. M. Fernández, D. Giannacopoulos, and W. J. Gross, “Multicore Acceleration of CG Algorithms Using Blocked-Pipeline-Matching Techniques”, Proceedings of IEEE Conference on the Computation of Electromagnetic Fields (COMPUMAG), November 22-26, 2009, pp. 827-828, Florianopolis, BRA.

  • K. Cushon, W. J. Gross, and S. Mannor, “Bidirectional Interleavers for LDPC Decoders using Transmission Gates”, Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), October 2009, pp. 232-237, Tampere, FIN. (doi)

  • G. Sarkis, S. Mannor, and W. J. Gross, “Stochastic Decoding of LDPC Codes over GF(q)”, Proceedings of IEEE International Conference on Communications (ICC), June 14-18, 2009, pp. 1-5, Dresden, DEU. (doi)

  • B. Sivasubramanian, W. J. Gross, and H. Leib, “Design and FPGA Implementation of Iterative Decoders for Codes on Graphs”, Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), May 3-6, 2009, pp. 1080-1084, St. John's, NF, CAN. (doi)

  • S. Sharifi Tehrani, A. Naderi, G.-A. Kamendje, S. Mannor, and W. J. Gross, “Tracking Forecast Memories in Stochastic Decoders”, Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), April 19-24, 2009, pp. 561-564, Taipei, TWN. (doi)

2008

  • D. M. Fernández, D. Giannacopoulos, and W. J. Gross, “Efficient Multicore Sparse Matrix-Vector Multiplication for Finite-Element Electromagnetics”, Proceedings of 13th Biennial IEEE Conference of Electromagnetic Field Computation (CEFC), May 11-15, 2008, p. 469, Athens, GRC.

  • A. J. Wong and W. J. Gross, “Configurable Flow Models for FPGA Particle Graphics Engines”, Proceedings of 16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 14-15, 2008, pp. 283-284, Palo Alto, CA, USA. (doi)

  • F. Côté, I. Psaromiligkos, and W. J. Gross, “On the Statistical Properties of GNSS Modulation”, Proceedings of Institute of Navigation National Technical Meeting (NTM), January 28-30, 2008, pp. 629-635, San Diego, CA, USA. (url)

2007

  • S. Sharifi Tehrani, S. Mannor, and W. J. Gross, “An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding”, Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), October 17-19, 2007, pp. 255-260, Shanghai, CHN. (doi)

  • J. J. Koo, A. C. Evans, and W. J. Gross, “Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer”, Proceedings of International Conference on Field Programmable Logic and Applications (FPL), August 27-29, 2007, pp. 11-16, Amsterdam, NLD. (doi)

  • L. Boulianne, M. Dumontier, and W. J. Gross, “A Stochastic Particle-Based Biological System Simulator”, Proceedings of SCS/ACM Summer Simulation Conference (SCSC), July 15-18, 2007, pp. 794-801, San Diego, CA, USA. (url)

  • J. J. Koo, D. M. Fernández, F. A. Haddad, and W. J. Gross, “Evaluation of a High-Level-Language Methodology for High-Performance Reconfigurable Computers”, Proceedings of IEEE 18th International Conference on Application-Specific Systems, Architectures, and Processors (ASAP), July 8-11, 2007, pp. 30-35, Montréal, QC, CAN. (doi)

  • C. Jego and W. J. Gross, “Turbo Decoding of Product Codes based on the Modified Adaptive Belief Propagation Algorithm”, Proceedings of IEEE International Symposium on Information Theory (ISIT), June 24-29, 2007, pp. 641-644, Nice, FRA. (doi)

  • S. Sharifi Tehrani, S. Mannor, and W. J. Gross, “Survey of Stochastic Computation on Factor Graphs”, Proceedings of 37th International Symposium on Multiple-Valued Logic (ISMVL), May 14-15, 2007, p. 54, Oslo, NOR. (doi)

  • J. S. Beeckler and W. J. Gross, “A Methodology for Prototyping Flexible Embedded Systems”, Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), April 22-26, 2007, pp. 1679-1682, Vancouver, BC, CAN. (doi)

2006

  • V. C. Gaudet and W. J. Gross, “On Density Evolution and Dynamic Power Estimation in Stochastic Iterative Decoders”, Proceedings of 5th Analog Decoding Workshop, June 5-6, 2006, pp. 43-46, Torino, ITA.

  • Y. El-Kurdi, W. J. Gross, and D. Giannacopoulos, “Hardware Acceleration for Finite Element Electromagnetics: Efficient Sparse Matrix Floating-Point Computations with Field Programmable Gate Arrays”, Proceedings of 12th Biennial IEEE Conference on Electromagnetic Field Computation (CEFC), April 30 - May 3, 2006, pp. 397-397, Miami, FL, USA. (doi)

  • Y. El-Kurdi, W. J. Gross, and D. Giannacopoulos, “Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs”, Proceedings of 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 24-26, 2006, pp. 293-294, Napa, CA, USA. (doi)

Prior to 2006

  • L. Boulianne and W. J. Gross, “SIMD Implementation of Interpolation in Algebraic Soft-Decision Reed-Solomon Decoding”, Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), November 2-4, 2005, pp. 750-755, Athens, GRC. (doi)

  • W. J. Gross, V. C. Gaudet, and A. Milner, “Stochastic Implementation of LDPC Decoders”, Proceedings of Conference Record of the 39th Asilomar Conference on Signals, Systems and Computers, October 30 - November 2, 2005, pp. 713-717, Pacific Grove, CA, USA. (doi)

  • S. Bi and W. J. Gross, “Efficient Residue Comparison Algorithm for General Moduli Sets”, Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 7-10, 2005, pp. 1601-1604, Cincinnati, OH, USA. (doi)

  • S. Bi, W. J. Gross, W. Wang, A. Al-Khalili, and M. N. S. Swamy, “An Area-Reduced Scheme for Modulo 2^n-1 Addition/Subtraction”, Proceedings of 5th International Workshop on System-on-Chip for Real-Time Applications (IWSOC), July 20-24, 2005, pp. 396-399, Banff, AB, CAN. (doi)

  • J. S. Beeckler and W. J. Gross, “FPGA Particle Graphics Hardware”, Proceedings of 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 17-20, 2005, pp. 85-94, Napa, CA, USA. (doi)

  • W. J. Gross, F. R. Kschischang, and P. G. Gulak, “An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding”, Proceedings of 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 20-23, 2004, pp. 310-311, Napa, CA, USA. (doi)

  • W. J. Gross, F. R. Kschischang, R. Koetter, and P. G. Gulak, “A VLSI Architecture for Interpolation in Soft-Decision List Decoding of Reed-Solomon Codes”, Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), October 16-18, 2002, pp. 39-44, San Diego, CA, USA. (doi)

  • W. J. Gross, F. R. Kschischang, R. Koetter, and P. G. Gulak, “Simulation Results for Algebraic Soft-Decision Decoding of Reed-Solomon Codes”, Proceedings of 21st Biennial Symposium on Communications, June 2-5, 2002, pp. 356-360, Queen's University, Kingston, ON, CAN.

  • W. J. Gross, V. C. Gaudet, and P. G. Gulak, “A VLSI Architecture for Soft-Output PR4 Detection”, Proceedings of IEEE 43rd Midwest Symposium on Circuits and Systems, vol. 1, August 8-11, 2000, pp. 416-419, Lansing, MI, USA. (doi)

  • E. Boutillon, W. J. Gross, and P. G. Gulak, “Gestion de la memoire pour l'algorithme du forward-backward”, Proceedings of 5eme Workshop AAA sur l'Adequation Algorithme Architecture, January 26-28, 2000, pp. 26-28, INRIA Rocquencourt, FRA.

  • V. R. Neralla, R. O. Ramseier, and W. J. Gross, “Utility of Passive Observations for Operational Sea Ice Modelling”, Proceedings of 3rd International Offshore and Polar Engineering Conference, June 6-11, 1993, pp. 600-606, Singapore, SGP.



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